CVE-2018-5407

unknown

Published — · Modified —

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CVSS v3

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CVSS v4 NEW

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not yet in upstream

VIR risk

1.0

Description

Simultaneous Multi-threading (SMT) in processors can enable local users to exploit software vulnerable to timing attacks via a side-channel timing attack on 'port contention'.

Predictions

Exploit likelihood

20%

Patch ETA

—

Heuristic predictions, AS-IS, for prioritization only.

Mitigations

No mitigations published for this CVE yet.

The vendor-content worker queues fetches as references arrive (check back in a few minutes). Or — if you've already worked around this in production — publish your fix to the community-verified tier.

✚ Propose a mitigation on Community → Mitigations published via the community go through AI scoring + 2 human reviewers + 7-day silent objection window before landing here with source_tier=community-verified.

Exploits

Public proof-of-concept code below. AS-IS, for defenders and authorised testing only.

Exploit-DB

EDB-45785 local hardware

Billy Brumley · 2018-11-02

Intel (Skylake / Kaby Lake) - 'PortSmash' CPU SMT Side-Channel

Source code queued for fetch — refresh in a moment.

OS impact

SUSE Affected 1 release

Version	Status	Fixed in
—	Affected	—

Debian Fixed 5 releases

Version	Status	Fixed in
trixie	Fixed	`1.1.1~~pre9-1`
sid	Fixed	`1.1.1~~pre9-1`
forky	Fixed	`1.1.1~~pre9-1`
bullseye	Fixed	`1.1.1~~pre9-1`
bookworm	Fixed	`1.1.1~~pre9-1`

References

Community-verified mitigations for this CVE will appear above when contributors publish them.

Verify integrity in audit chain (admin only). AS-IS.